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HD-LINX TM GS1500
HDTV Serial Digital Deformatter with ANC FIFOs
PRELIMINARY DATA SHEET FEATURES * SMPTE 292M compliant * standards detection/indication for SMPTE 292M levels A/B,C,D/E,F,G/H,I,J/K,L/M * NRZI decoding and SMPTE descrambling with BYPASS option * line CRC calculation, comparison * selectable line based CRC re-insertion * H, V, F timing reference signal (TRS) extraction * selectable flywheel for noise immune H, V, F extraction * selectable automatic switch line handling * selectable TRS and line number re-insertion * selectable active picture illegal code re-mapping * ANC data position indication * ANC data extraction via internal FIFOs (1024 bytes on Y and C channels) * configurable FIFO LOAD pulse * 20 bit 3.3V CMOS input data bus * optimized input interface to GS1545 or GS1540 * single +3.3V power supply * 5V tolerant I/O APPLICATIONS SMPTE 292M Serial Digital Interfaces. ORDERING INFORMATION
PART NUMBER GS1500-CQR PACKAGE 128 pin MQFP TEMPERATURE 0C to 70C
DESCRIPTION When interfaced to the Gennum GS1545 HDTV Equalizing Receiver or GS1540 Non-Equalizing Receiver, the GS1500 performs the final conversion to word aligned data. The device performs NRZI decoding and de-scrambling as per SMPTE 292M and word-aligns to the incoming data stream. Line based CRCs are calculated on the incoming data stream and are compared against the CRCs embedded within the data stream. HVF timing information is extracted from the data stream. A selectable internal HVF flywheel provides superior noise immunity against TRS signal errors. The device also detects and indicates the input video signal standard. The GS1500 can detect and re-map illegal code words contained within the active portion of the video signal. The positions of the embedded ANC data are indicated and the ANC data may be extracted and accessed by the user through an internal FIFO interface. Prior to exiting the device, TRS, Line Numbers and CRCs based on internal calculations may be re-inserted into the data stream.
GS1500
WB_NI BP_DSC BP_FR 3
FW_EN/DIS FAST_LOCK 2 RESET
TRS_Y/C F_E/S 2 MUTE
EX/CP CODE PROTECT
FM_I/E R_CLK 2 ANC/DATA
ANC_Y/C
TRS_INS LN_INS CRC_INS 3 DATA_OUT [19:10] (LUMA)
DATA_IN [19:0] INPUT BUFFER DESCRAMBLE FRAME
TRS DETECTION FLYWHEEL STANDARD DETECTION TRS EXTRACTION CRC
CALCULATION
ILLEGAL CODE REMAPPING ANC DATA DETECTION & EXTRACTION FIFO'S
CRC COMPARISON
TRS, LNUM, AND CRC INSERTION
DATA_OUT [9:0] (CHROMA)
PCLK_IN 3 2 FF_STA 2 FFRST 2 [2:0] FOEN ANC_DATA YCS_ERR REN [Y:C] CCS_ERR WEN 2
3 [H:V:F] 3 FIFO_L 4 2
10
ANC_OUT [9:0]
OEN
LN_ERR SAV_ERR EAV_ERR
VD_STD [3:0]
LINE_CRC_ERR[Y:C]
BLOCK DIAGRAM
Revision Date: November 2000 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 522 - 33 - 00
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering 10 seconds) VALUE -0.5V to +4.6V -0.5V < VIN < 5.5V 0C TA 70C
GS1500
-40C TS 125C 260C
DC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6V, TA = 0C to 70C, unless otherwise shown
PARAMETER Positive Supply Voltage Supply Current Input Logic LOW Voltage Input Logic HIGH Voltage Output Logic LOW Voltage Output Logic HIGH Voltage
SYMBOL VDD DD VIL VIH VOL VOH
CONDITIONS
MIN 3.0
TYP 3.3 402 3.3 0.2 -
MAX 3.6 480 0.8 5.0 0.4 -
UNITS V mA V V V V
NOTES
= 74.25MHz, TA = 25C ILEAKAGE < 10A ILEAKAGE < 10A VDD = 3.0 to 3.6V, IOL= 4mA VDD = 3.0 to 3.6V, IOH= -4mA
2.1 2.6
AC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6V, TA = 0C to 70C
PARAMETER Clock Input Frequency Input Data Setup Time Input Data Hold Time Input Clock Duty Cycle Output Data Hold Time Output Enable Time Output Disable Time Output Data Delay Time Output Data Rise/Fall Time FIFO Input Data Setup Time FIFO Input Data Hold Time NOTES:
SYMBOL HSCI tSU tIH
CONDITIONS
MIN 2.5 1.5 40
TYP 74.25 -
MAX 80 60 8 9 10 2.5 -
UNITS MHz ns ns % ns ns ns ns ns ns ns Note 2 Note 3
NOTES Also supports 74.25/1.001MHz 50% levels 50% levels
tOH tOEN tODIS tOD tROD/tFOD tFSU tFIH
With 15pF load With 15pF load With 15pF load With 15pF load With 15pF load
2.0 8.0 4.0
20% to 80% levels Note 1 Note 1
1. The following signals need to adhere to this timing: ANC_Y/C, REN, WEN, FFRST 2. Timing of the FF_STA[2:0] outputs may be greater than specified. 3. Output timing characteristics also apply to FIFO outputs.
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PIN CONNECTIONS
DATA_OUT[19] DATA_OUT[18] DATA_OUT[17] DATA_OUT[16] DATA_OUT[15] VDD GND DATA_OUT[14] DATA_OUT[13] DATA_OUT[12] DATA_OUT[11] DATA_OUT[10] DATA_OUT[9] VDD GND DATA_OUT[8] DATA_OUT[7] VDD GND DATA_OUT[6] DATA_OUT[5] DATA_OUT[4] DATA_OUT[3] DATA_OUT[2] DATA_OUT[1] DATA_OUT[0]
GS1500
LN_ERR SAV_ERR EAV_ERR VDD GND TEST YCS_ERR CCS_ERR FF_STA[0] FF_STA[1] FF_STA[2] ANC_OUT[9] ANC_OUT[8] VDD GND ANC_OUT[7] VDD GND ANC_OUT[6] ANC_OUT[5] ANC_OUT[4] ANC_OUT[3] ANC_OUT[2] ANC_OUT[1] ANC_OUT[0] VDD GND R_CLK VDD GND FOEN FFRST WEN REN ANC/DATA FM_I/E ANC_Y/C EX/CP
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 GS1500 TOP VIEW 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VDD GND OEN TN FIFO_L LINE_CRC_ERR_Y LINE_CRC_ERR_C VD_STD[0] VD_STD[1] VD_STD[2] VD_STD[3] ANC_DATA_C ANC_DATA_Y VDD GND F V H VDD GND RESET FAST_LOCK CRC_INS LN_INS GND TRS_INS TRS_Y/C WB_NI BP_DSC BP_FR CODE_PROTECT FW_EN/DIS MUTE F_E/S GND VDD GND PCLK_IN
VDD GND DATA_IN[13] DATA_IN[12] DATA_IN[11] DATA_IN[10]
DATA_IN[19] DATA_IN[18] DATA_IN[17] DATA_IN[16] DATA_IN[15] DATA_IN[14]
VDD GND DATA_IN[9] DATA_IN[8] DATA_IN[7] DATA_IN[6] DATA_IN[5] DATA_IN[4] DATA_IN[3] DATA_IN[2] DATA_IN[1] DATA_IN[0]
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PIN DESCRIPTIONS
NUMBER 1 SYMBOL PCLK_IN TIMING Synchronous wrt PCLK_IN TYPE Input DESCRIPTION Input Clock. The device uses PCLK_IN for clocking the input data stream into DATA_IN[19:0]. This clock is generated by the GS1545 or GS1540. Ground power supply connections.
2, 4, 14, 19, 24, 37, 46, 50, 58, 69, 79, 82, 91, 94, 110, 116, 128 3, 20, 25, 38, 47, 51, 59, 68, 78, 81, 90, 93, 109, 115, 127 5
GND
GND
GS1500
VDD
Power
Positive power supply connections.
F_E/S
Nonsynchronous
Input
Control Signal Input. Used to control where the FIFO_L signal is generated. When F_E/S is high, the GS1500 generates FIFO_L signal at EAV. When F_E/S is low, the GS1500 generates FIFO_L signal at SAV. See Fig. 4 for timing information. Control Signal Input. Used to enable or disable blanking of the LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT[9:0]). When MUTE is low, the device sets the accompanying LUMA and CHROMA data to their appropriate blanking levels. When MUTE is high, the LUMA and CHROMA data streams pass through this stage of the device unaltered. Control Signal Input. Used to enable or disable the internal flywheel. When FW_EN/DIS is high, the internal flywheel is enabled. When FW_EN/DIS is low, the internal fly-wheel is disabled. Control Signal Input. Used to enable or disable re-mapping of outof -range words contained in the active portion of the video signal. When this signal is high, the device re-maps out-of-range words contained within the active portion of the video signal into CCIR-601 compliant words. Values between 000-003 are re-mapped to 004. Values between 3FC and 3FF are re-mapped to 3FB. When this signal is low, out-of-range words in the active video region pass through the device unaltered. Control Signal Input. Used to enable or disable word boundary framing. When BP_FR is low, internal framing is enabled. When BP_FR is high, internal framing is bypassed. Control Signal Input. Used to enable or disable the SMPTE 292M descrambler. When BP_DSC is low, the internal SMPTE 292M descrambler is enabled. When BP_DSC is high, the internal SMPTE 292M de-scrambler is bypassed. Control Signal Input. Used to enable or disable noise immune operation of the word boundary framer. When WB_NI is high, noiseimmune word boundary alignment is enabled. The device switches to a new word boundary only when it has detected two consecutive identical new TRS positions. When WB_NI is low, the device realigns the word boundary position at every instance of a TRS. Control Signal Input. Used to control whether LUMA or CHROMA TRS ID's are detected and used. When TRS_Y/C is high, the device detects and uses TRS signals embedded in the LUMA channel. When TRS_Y/C is low, the device detects and uses TRS signals embedded in the CHROMA channel.
6
MUTE
Synchronous wrt PCLK_IN
Input
7
FW_EN/DIS
Nonsynchronous
Input
8
CODE_PROTECT
Nonsynchronous
Input
9
BP_FR
Nonsynchronous
Input
10
BP_DSC
Nonsynchronous
Input
11
WB_NI
Nonsynchronous
Input
12
TRS_Y/C
Nonsynchronous
Input
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PIN DESCRIPTIONS (Continued)
NUMBER 13 SYMBOL TRS_INS TIMING Nonsynchronous TYPE Input DESCRIPTION Control Signal Input. Used to enable or disable re-insertion of the TRS into the data stream. When TRS_INS is high, the device reinserts TRS into the incoming data stream based on the internal calculation. The original TRS packets are set to the blanking levels. If the flywheel is enabled, TRS calculated by the flywheel is used for insertion. When TRS_INS is low, the device will not re-insert TRS even if errors in TRS signals are detected. Control Signal Input. Used to enable or disable re-insertion of the line number into the data stream. When LN_INS is high, the device re-inserts the line number into the incoming data stream based on the internal calculation. The original line number packets are set to the blanking levels. If the flywheel is enabled, the line number calculated by the flywheel is used for insertion. When LN_INS is low, the device will not re-insert the line number. Control Signal Input. Used to enable or disable re-insertion of the CRC into the data stream. When CRC_INS is high, the device is enabled to re-insert line CRCs based on the internal calculation. When CRC_INS is low, the device will not re-insert the CRCs. Control Signal Input. Used to control the flywheel synchronization when a switch line occurs. When a low to high transition occurs on the FAST_LOCK signal, the internal flywheel will immediately resynchronize to the next valid EAV or SAV TRS in the incoming data stream. See Fig. 5 for timing information. Control Signal Input. Used to reset the system state registers to their default 720p parameters. When RESET is high, the fly wheel, TRS Detection, and ANC Detection operate normally. When RESET is low, the flywheel, TRS Detection, and ANC Detection are reset to the 720p parameters after a rising edge on PCLK_IN. The read and write counters are not affected. Control Signal Output. This signal indicates the Horizontal blanking period of the video signal. Refer to Fig. 2 for timing information of H relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA respectively. Control Signal Output. This signal indicates the Vertical blanking period of the video signal. Refer to Fig. 2 for timing information of V relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA respectively. Control Signal Output. This signal indicates the ODD/EVEN field of the video signal. Refer to Fig. 2 for timing information of F relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA respectively. When locked and the input signal is of a progressive scan nature, F stays low at all times. Control Signal Output. This signal indicates the position of the embedded ANC data in the outgoing LUMA (DATA_OUT [19:10]) data stream. ANC_DATA_Y goes high for the entire time that an ANC_DATA packet is present in the LUMA (DATA_OUT[19:10]) data stream whether it be in the active video area or the ANC area. Refer to Fig. 17 for timing of ANC_DATA_Y relative to LUMA (DATA_OUT[19:10]). During detection of ANC data, any errors in the data count (DC) packet will consequently cause errors in the duration of the flags. Bit errors in an ANC header will prevent the packet from being detected.
GS1500
15
LN_INS
Nonsynchronous
Input
16
CRC_INS
Nonsynchronous
Input
17
FAST_LOCK
Synchronous wrt PCLK_IN
Input
18
RESET
Nonsynchronous
Input
21
H
Synchronous wrt PCLK_IN
Output
22
V
Synchronous wrt PCLK_IN
Output
23
F
Synchronous wrt PCLK_IN
Output
26
ANC_DATA_Y
Synchronous wrt PCLK_IN
Output
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PIN DESCRIPTIONS (Continued)
NUMBER 27 SYMBOL ANC_DATA_C TIMING Synchronous wrt PCLK_IN TYPE Output DESCRIPTION Control Signal Output. This signal indicates the position of the embedded ANC data in the outgoing CHROMA (DATA_OUT[9:0]) data stream. ANC_DATA_C goes high for the entire time that an ANC_DATA packet is present in the CHROMA (DATA_OUT[9:0]) data stream whether it be in the active video area or the HANC area. Refer to Fig. 17 for timing of ANC_DATA_C relative to CHROMA (DATA_OUT[9:0]). During detection of ANC data, any errors in the data count (DC) packet will consequently cause errors in the duration of the flags. Bit errors in an ANC header will prevent the packet from being detected. Control Signal Output. VD_STD[3:0] indicates which input video standard the device has detected. The GS1500 will indicate all of the formats in SMPTE292M (see Table 3) plus it will indicate an unknown interlace or progressive scan format. Status Signal Output. Indicates a difference in the calculated versus embedded CRC in the CHROMA channel. When LINE_CRC_ERR_C is high, it indicates that the GS1500 has detected a difference between the line based CRCs it calculates for the CHROMA channel and the line based CRCs embedded within the CHROMA channel. When LINE_CRC_ERR_C is low, the embedded and calculated CRC's match. Refer to Fig. 19 for timing information of LINE_CRC_ERR_C. Status Signal Output. Indicates a difference in the calculated versus embedded CRC in the LUMA channel. When LINE_CRC_ERR_Y is high, it indicates that the GS1500 has detected a difference between the line based CRCs it calculates for the LUMA channel and the line based CRCs embedded within the LUMA channel. When LINE_CRC_ERR_Y is low, the embedded and calculated CRC's match. Refer to Fig. 19 for timing information of LINE_CRC_ERR_Y. Control Signal Output. Used to control an external FIFO(s). FIFO_L is normally high, but is set low for the EAV or SAV word depending on the state of F_E/S. Refer to Fig. 4 for timing information of FIFO_L relative to LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT[9:0]). Test Pin. Used for test purposes only. This pin must be connected to VDD for normal operation Control Signal Input. Used to enable the DATA_OUT[19:0] output bus or set it in a high Z state. When OEN is low, the LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]) busses are enabled. When OEN is high, these busses are in a high Z state. CHROMA Output Data Bus. DATA_OUT [9] is CHROMA_OUT[9] which is the MSB of the CHROMA output signal (pin 52). DATA_OUT [0] is CHROMA_OUT[0] which is the LSB of the CHROMA output signal (pin 39). LUMA Output Data Bus. DATA_OUT [19] is LUMA_OUT[9] which is the MSB of the LUMA output signal. (pin 64) DATA_OUT [10] is LUMA_OUT[0] which is the LSB of the LUMA output signal (pin 53). Status Signal Output. Used to indicate a Line Number error or a mismatch between the embedded line number and the flywheel line number when the flywheel is enabled. When LN_ERR is high, a line number error is detected or the internal flywheel indicates mismatching line numbers. Refer to Fig. 3 for timing information of LN_ERR relative to LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]) Since LN_ERR depends on the sequence of line numbers, a line number error will actually cause LN_ERR to go high for two lines.
GS1500
28, 29, 30, 31
VD_STD[3:0]
Synchronous wrt PCLK_IN
Output
32
LINE_CRC_ERR_C
Synchronous wrt PCLK_IN
Output
33
LINE_CRC_ERR_Y
Synchronous wrt PCLK_IN
Output
34
FIFO_L
Synchronous wrt PCLK_IN
Output
35
TN
TEST
36
OEN
Nonsynchronous
Input
39, 40, 41, 42, 43, 44, 45, 48, 49, 52
DATA_OUT[9:0] (CHROMA channel) DATA_OUT[19:10] (LUMA channel) LN_ERR
Synchronous wrt PCLK_IN
Output
53, 54, 55, 56, 57, 60, 61, 62, 63, 64 65
Synchronous wrt PCLK_IN
Output
Synchronous wrt PCLK_IN
Output
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PIN DESCRIPTIONS (Continued)
NUMBER 66 SYMBOL SAV_ERR TIMING Synchronous wrt PCLK_IN TYPE Output DESCRIPTION Status Signal Output. Indicates a TRS error or a mismatch between the embedded TRS and the flywheel TRS when the flywheel is enabled. This signal is set high when an error in the SAV TRS is detected or when the internal flywheel indicates there is a mismatching SAV TRS. Refer to Fig. 3 for timing information of SAV_ERR relative to LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]). Status Signal Output. Indicates a TRS error or a mismatch between the embedded TRS and the flywheel TRS when the flywheel is enabled. This signal is set high when an error in the EAV TRS is detected or when the internal flywheel indicates there is a mismatching EAV TRS. Refer to Fig. 3 for timing information of EAV_ERR relative to LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]). Test Pin. Used for test purposes only. This pin must be connected to GND for normal operation. Status Signal Output. Indicates a checksum error or a mismatch between the embedded checksum and the calculated checksum for the LUMA (DATA_OUT[19:10]) channel. When YCS_ERR is high, an error in the checksum is detected. Refer to Fig. 18 for timing information of YCS_ERR relative to LUMA (DATA_OUT[19:10]). Status Signal Output. Indicates a checksum error or a mismatch between the embedded checksum and the calculated checksum for the CHROMA (DATA_OUT[9:0]) channel. When CCS_ERR is high, an error in the checksum is detected. Refer to Fig. 18 for timing information of CCS_ERR relative to CHROMA (DATA_OUT [9:0]). Control Signal Output. FF_STA[2:0] is the FIFO status output to indicate the content level of the internal FIFOs. FF_STA[2:0]=000: Error flag, FIFO is under run . FF_STA[2:0]=001: FIFO is empty. FF_STA[2:0]=010: FIFO is almost empty; 32 bytes filled FF_STA[2:0]=011: FIFO is ready. FF_STA[2:0]=100: FIFO is half full. FF_STA[2:0]=101: FIFO is almost full; 992 bytes filled FF_STA[2:0]=110: FIFO is full. FF_STA[2:0]=111: Error flag, FIFO is over run. When ANC_Y/C is high, FF_STA[2:0] indicates the status of the LUMA ANC data FIFO. When ANC_Y/C is low, FF_STA[2:0] indicates the status of the CHROMA ANC data FIFO. See Fig. 6 to Fig. 15 for timing information. 76, 77, 80, 83, 84, 85, 86, 87, 88, 89 ANC_OUT[9:0] Synchronous wrt PCLK_IN Output ANC Data Output Bus. ANC_OUT[9] is the MSB and ANC_OUT[0] is the LSB. When ANC_Y/C is high, ANC_OUT[9:0] presents ANC data from the LUMA FIFO. When ANC_Y/C is low, ANC_OUT[9:0] presents ANC data from the CHROMA FIFO. Input Clock Signal. Used to read information from the internal FIFO(s). On the rising edge of R_CLK, the device will extract the next word from the internal LUMA/CHROMA channel data FIFO, depending on the status of the ANC_Y/C signal. Control Signal Input. Used to enable or disable the internal FIFO outputs. When FOEN is low, the FIFO ANC_OUT[9:0] and FF_STA[2:0] are enabled. When FOEN is high, the FIFO ANC_OUT[9:0] and FF_STA[2:0] outputs are in a high Z state. Note that the internal read address pointers are updated independently of FOEN.
GS1500
67
EAV_ERR
Synchronous wrt PCLK_IN
Output
70
TEST
TEST
71
YCS_ERR
Synchronous wrt PCLK_IN
Output
72
CCS_ERR
Synchronous wrt PCLK_IN
Output
73, 74, 75
FF_STA[2:0]
Output
92
R_CLK
N/A
Input
95
FOEN
Nonsynchronous
Input
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PIN DESCRIPTIONS (Continued)
NUMBER 96 SYMBOL FFRST TIMING Synchronous wrt PCLK_IN TYPE Input DESCRIPTION Control Signal Input. FFRST is used to supply synchronous reset signals to the FIFO. When FFRST is low, the FIFO is reset and all internal read and write address pointers are set to their starting locations. Control Signal Input. Used to enable or disable extracting data into the internal FIFO. When WEN is low, extracting data into the internal FIFO is enabled. When WEN is high, extracting data into the internal FIFO is disabled. Control Signal Input. Used to enable or disable reading data from the internal FIFO. When REN is low, reading from the internal FIFO is enabled. When REN is high, reading from the internal FIFO is disabled. Control Signal Input. Used to control copying of ANC data packets into the internal FIFOs. When ANC/DATA is high, the device extracts/copies only ANC data packets into the internal FIFO buffers. When ANC/DATA is low, the device extracts/copies all data words within the horizontal blanking period regardless of their status (i.e. ANC data or not) and places these words into the internal FIFO buffers. Control Signal Input. When FM_I/E is high, the device operates in a mode where the FIFO reset and write enable signals are generated internally. In this mode, the device limits the data extraction to the HANC region of the video stream. The extracted ANC data are to be accessed during the active video period using REN. When FM_I/E is low, the device operates in another mode where the FIFO reset and write enable signals are generated externally by the user and supplied to the device via the FFRST and WEN control signal inputs. Control Signal Input. Used to control extraction of ANC data from the video data stream into the LUMA or CHROMA FIFO. When ANC_Y/C is high, data is extracted from the luma data stream into the internal LUMA FIFO. When ANC_Y/C is low, data is extracted from the chroma data stream into the internal CHROMA FIFO. Control Signal Input. Used to control if the ANC Data is extracted or copied into the internal FIFO buffers. When EX/CP is high, the device extracts ANC data from the incoming data stream into the internal FIFO buffers and replaces any extracted words with appropriate blanking levels. When EX/CP is low, the device makes a copy of ANC data from the incoming data stream into the internal FIFO buffers. Input Data Bus. DATA_IN [19] is the MSB of the signal (pin 103). DATA_IN [0] is the LSB of the signal (pin 126). This data is typically scrambled and not word aligned.
97
WEN
Synchronous wrt PCLK_IN
Input
GS1500
98
REN
Synchronous wrt R_CLK
Input
99
ANC/DATA
Nonsynchronous
Input
100
FM_I/E
Nonsynchronous
Input
101
ANC_Y/C
Synchronous wrt PCLK_IN
Input
102
EX/CP
Nonsynchronous
Input
103,104,105, 106, 107, 108, 111, 112, 113, 114, 117, 118, 119,120, 121, 122, 123, 124, 125, 126
DATA_IN [19:0]
Synchronous wrt PCLK_IN
Input
DETAILED DESCRIPTION
1. DATA INPUT AND OUTPUTS
2. DESCRAMBLER AND FRAMER
Data enters and exits the device on the rising edge of PCLK_IN as shown in Figures 1 and 2. This data can be scrambled or unscrambled and framed or unframed.
Both the descrambler and framer can be enabled or disabled independently to allow the input to remain scrambled or unscrambled. If the data is unscrambled, it can be word aligned (framed) or pass through unaltered.
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3. STANDARDS INDICATION
VD_STD[3:0] indicates the standard that the device has detected. The states of VD_STD[3:0] are shown Tables 1 and 2.
TABLE 1. Progressive Scan Standards Indication (VD_STD[3]=0) VD_STD[3:0] 0000 0001 0010 DESCRIPTION 720p (60 & 60/1.001Hz L/M) [SMPTE296M] Reserved 1080p (30 & 30/1.001Hz G/H) [SMPTE274M] Reserved 1080p (25Hz I) [SMPTE274M] Reserved 1080p (24 & 24/1.001Hz J/K) [SMPTE274M] Unknown Progressive with F = 0 always.
consecutive lines having identical timing are detected, this new timing information is saved and the flywheel operation is updated to this new timing. Mismatches between the HVF information decoded from the data stream and that indicated by the flywheel will trigger the EAV_ERR and SAV_ERR signals as shown in Figure 3. HVF output timing is shown in Figure 2.
GS1500
5. AUTOMATIC SWITCH LINE LOCK HANDLING
0011 0100 0101 0110 0111
The automatic switch line lock is based on the assumption that switching occurs between video sources of the same format. In other words, the switching of video sources causes only the H signal to be out of alignment whereas V and F signals remain in sync. Therefore, when in the automatic switch line lock mode (FAST_LOCK transitions for low to high), the flywheel positive H signal transition aligns with the detected positive H signal transition. Timing for the FAST_LOCK signal is shown in Figure 5.
6. FIFO
TABLE 2. Interlaced Standards Indication (VD_STD[3]=1) VD_STD[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 DESCRIPTION 1080i (30 & 30/1.001Hz D/E) [SMPTE274M] Reserved 1080i (25Hz F) [SMPTE274M] Reserved 1080i (25Hz C) [SMPTE295M] Reserved 1035i (30 & 30/1.001Hz A/B) [SMPTE260M] Unknown Interlaced with F switching 0/1
The device does not flag transmission errors which might exist in the ANC data packages. The internal FIFO is 1024 words deep for each of LUMA and CHROMA channels. For those formats where the HANC region is greater than 1024 words, the user must take steps to ensure the FIFO does not overflow, otherwise data may be lost. The GS1500 provides status signals to indicate the current content level of the internal FIFO buffers, as described in section 6.1.
6.1. FIFO Status Bits
The device provides status output signals FF_STA[2:0] that indicate the state of the current content level of the internal FIFO buffers. If the extracted ANC data have completely filled the internal FIFO buffer, FF_STA[2:0] outputs 110. When the internal FIFO is full, any attempt to write data into the FIFO will cause the FIFO to overrun. The device flags this overrun state by setting FF_STA[2:0]=111 and no more data will be extracted from the video stream. If all ANC data in the FIFO is accessed by the user through the FIFO interface and the internal FIFO becomes empty, then FF_STA[2:0] outputs 001. When the internal FIFO is empty, any attempt to read data from the FIFO will cause the FIFO to under run. The device flags this under run state by setting FF_STA[2:0]=000. When ANC_Y/C is high, FF_STA indicates the status of the LUMA FIFO buffer. When ANC_Y/C is low, FF_STA indicates the status of the CHROMA FIFO buffer. The FIFO status flags must be up-to-date. Therefore, certain FIFO status flags are synchronized with respect to R_CLK, and others are synchronized with respect to PCLK_IN. During a write cycle, status flags controlled by R_CLK experience a three-cycle latency with respect to R_CLK. During a read cycle, status flags controlled by PCLK_IN experience a three-cycle latency with respect to PCLK_IN. See Table 4 and Figures 6 to 15. 9
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Note the following in the above Standards Indication Tables: * * * * SMPTE260M is 1125 lines/frame SMPTE274M is 1125 lines/frame SMPTE295M is 1250 lines/frame SMPTE296M is 750 lines/frame
See Table 3 for more details on the source format parameters.
4. FLY WHEEL OPERATION
The flywheel logic checks the incoming video data for valid video lines. If the incoming data represents a valid line, the flywheel remains in sync with the incoming data. If the incoming data represents an invalid line, the flywheel uses the stored timing information for the past valid line to generate the output HVF timing signals. When three
GENNUM CORPORATION
NOTE: If a simultaneous FIFO read and write operation is to be performed, the FF_STA[2:0] outputs should not be used as they may indicate incorrect FIFO status.
6.2. ANC/DATA Extraction
6.3. FIFO Read Control
When the control signal ANC/DATA is high and WEN is low, the device detects the ANC data header and extracts the ANC data (including the header) when these data are present in the video streams. When ANC/DATA and WEN are both low, the device extracts all original video data into the FIFO. To ensure ANC data extraction from the LUMA or CHROMA channels, empty (unload) the ANC data from the respective FIFO buffer during the active video portion of the data streams. ANC data is extracted from a video stream and written into the corresponding internal FIFO buffer until it is completely full. When a FIFO buffer is full, the FF_STA[2:0] signal is set to 110. The device provides ANC data copying capability as an alternative to extraction. When EX/CP is high, the extraction function is enabled. The device replaces the extracted data in the video streams with their respective blanking levels. If EX/CP is low, the copy function is enabled. All the original data remain in the video stream after copying them into the FIFO buffer. To extract ANC data from the HANC region only, the device provides an automated extraction mode. When the control signal FM_I/E is high, the FIFO control signals FFRST and WEN cannot be used. In this mode of operation, the device generates reset and enable signals internally, which allows an automated extraction of ANC data from HANC region of the incoming LUMA and CHROMA data streams. The user must supply a proper REN signal to enable the access of ANC data stored in the FIFO. These data should be read out of the FIFO during the active video period. Once all words have been read from the FIFO, the FF_STA signal is set to 001. If the user has not emptied the FIFO by the time the next HANC period begins, all data within the FIFO is discarded and the FIFO resets so that read and write address pointers are at their starting position. When the control signal FM_I/E is low, the user has full control over reading from and writing to the FIFO, including the FIFO reset (FFRST) and FIFO write enable (WEN). The ANC data output ANC_OUT[9:0] can be set to a high Z state with the FOEN control signal. When FOEN is low, the ANC_OUT[9:0] outputs are enabled. When FOEN is high, the ANC_OUT[9:0] outputs are in a high Z state. Internal read address pointers are incremented regardless of the state of FOEN when REN is low.
The FIFO control signal REN is the read enable signal used to access ANC data in the internal FIFO through the FIFO interface. The user can access only one of the two internal FIFO buffers at a time. The LUMA FIFO can be read when ANC_Y/C is high. The CHROMA FIFO can be read when ANC_Y/C is low.
GS1500
When the internal FIFO is not in the empty or underrun states, it is ready to provide ANC data to the user. At this point, the user should read up to 1024 data words from each FIFO through the FIFO interface. When REN is low and a rising edge on R_CLK is detected, the device outputs the next word stored in the FIFO. Each time R_CLK is toggled while REN is low, the internal read address pointer (LUMA or CHROMA) is incremented. When REN is high, the read address pointer is not incremented.
6.4. FIFO Write Control
The FIFO control signal WEN is the write enable signal. It enables the ANC data extraction from either the LUMA or the CHROMA video streams into the internal respective FIFO buffers. When WEN is LOW, the write address pointer increments with the internal clock at the video data rate. When WEN is HIGH, the write address pointer does not increment. To reset both address pointers for read and write to their starting positions, toggle the FIFO reset signal FFRST from high to low.
6.5. FIFO External Reset
In external FIFO control mode, the internal FIFO address pointers are reset to zero (0) using FFRST. A recommended external reset process is shown in Figure 16.
7. READING CRC ERROR FLAGS
The GS1500 provides error flags which track the Cyclic Redundancy Code embedded in each line of LUMA and CHROMA video streams (LINE_CRC_ERR_Y and LINE_CRC_ERR_C, respectively). NOTE: For users monitoring the status of the CRC error flags, it is strongly recommended that they are read only when FOEN is low.
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TABLE 3: Source Format Parameters Reference SMPTE Standard Format ID Lines/Frame Words/Active Line (each channel Y, Cb/Cr) Total Active Lines Words/Total Line (each channel Y, Cb/Cr) Frame Rate (Hz) Fields /Frame Data Rate Divisor NOTE: M=1.001 in the above table. 30 2 1 30/M 2 M 25 2 1 30 2 1 30/M 2 M 25 2 1 30 1 1 30/M 1 M 25 1 1 24 1 1 24/M 1 M 60 1 1 60/M 1 M 1035 2200 1035 2200 1080 2376 1080 2200 1080 2200 1080 2640 1080 2200 1080 2200 1080 2640 1080 2750 1080 2750 720 1650 720 1650 260m A 1125 1920 260m B 1125 1920 295m C 1250 1920 274m D 1125 1920 274m E 1125 1920 274m F 1125 1920 274m G 1125 1920 274m H 1125 1920 274m I 1125 1920 274m J 1125 1920 274m K 1125 1920 296m L 750 1280 296m M 750 1280
GS1500
TABLE 4: FIFO Status Indicator FF_STA[2:0] 000 001 010 011 100 101 110 111 DESCRIPTION ERROR Flag; FIFO is under run FIFO is empty FIFO is almost empty; <= 32 bytes filled FIFO is ready FIFO is half full FIFO is almost full; >= 992 bytes filled FIFO is full ERROR Flag; FIFO is over run SYNCHRONIZED TO R_CLK R_CLK R_CLK PCLK_IN PCLK_IN PCLK_IN PCLK_IN
PCLK_IN
DATA_IN
DATA
DATA
DATA
DATA
DATA
DATA_OUT
tSU tIH
DATA
DATA
tOH tOD
Fig. 1 Synchronous I/O Timing
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PCLK_IN DATA_OUT[19:10] (LUMA) DATA_OUT[9:0] (CHROMA) H
XYZ (EAV ID) XYZ (EAV ID) XYZ (SAV ID) XYZ (SAV ID)
3FF
000
000
YLN0
3FF
000
000
3FF
000
000
CLN0
3FF
000
000
GS1500
V F
Fig. 2 HVF Timing
PCLK_IN DATA_OUT (Luma or Chroma depending on the state of TRS_Y/C) EAV_ERR SAV_ERR
Correct/Incorrect ID 3FF 000 000 XYZ (EAV-ID) Correct/Incorrect Line Number LN0 LN1 3FF 000 Correct/Incorrect ID 000 XYZ (SAV-ID)
LN_ERR
Fig. 3 EAV_ERR, SAV_ERR and LN_ERR Timing
PCLK_IN DATA_OUT[19:10] (LUMA) DATA_OUT[9:0] (CHROMA) FIFO_L (F_E/S=1) FIFO_L (F_E/S=0)
XYZ (EAV-ID) XYZ (EAV-ID) XYZ (SAV-ID) XYZ (SAV-ID)
3FF
000
000
3FF
000
000
3FF
000
000
3FF
000
000
Fig. 4 FIFO_L Timing
DATA_IN (Luma or Chroma depending on the state of TRS_Y/C)
EAV
ANC SPACE
SAV Switch Line
ACTIVE PICTURE
EAV
ANC SPACE
SAV
ACTIVE PICTURE Switch Line + 1
FAST_LOCK
A Low to High Transition in the Active Picture of a Line Forces the GS1500 to Resynchronize to the next valid TRS ID
Fig. 5 FAST_LOCK Timing
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PCLK_IN REN
R_CLK
GS1500
ANC_OUT[9:0] FF_STA[2:0]
110 (Full)
WORD1
WORD2
WORD3
101 (Almost Full) WORD1 clocked out on this clock edge
1 R_CLK latency after REN goes low
Fig. 6 FIFO Full to Almost Full Read Timing
PCLK_IN REN
(Low)
R_CLK ANC_OUT[9:0] FF_STA[2:0]
WORD31
WORD32
WORD33
WORD34
WORD35
101 (Almost full)
100 (Half Full)
Fig. 7 FIFO Almost Full to Half Full Read Timing
PCLK_IN REN
(Low)
R_CLK ANC_OUT[9:0] FF_STA[2:0]
WORD511
WORD512
WORD513
WORD514
WORD515
100 (Half Full)
011 (Ready)
Fig. 8 FIFO Half Full to Ready Read Timing
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PCLK_IN REN
(Low)
R_CLK
GS1500
ANC_OUT[9:0] FF_STA[2:0]
WORD987
WORD988
WORD989
WORD990
WORD991
011 (Ready)
010 (Almost Empty)
Fig. 9 FIFO Ready to Almost Empty Read Timing
PCLK_IN REN
R_CLK ANC_OUT[9:0] FF_STA[2:0]
WORD 1019 WORD 1020 010 (Almost Empty) WORD 1021 WORD 1022 WORD 1023 WORD 1024 000 (Read Error) WORD 1025 WORD 1026 001 (Empty)
001 (Empty)
Fig. 10 FIFO Almost Empty to Empty to Read Error Read Timing
PCLK_IN DATA_OUT[19:10] (LUMA) WEN
3FF
000
000
XYZ (EAV-ID)
LN0
LN1
YCRC0
YCRC1
WORD1
WORD2
WORD3
7 Cycles (Will write data beginning at Word 1)
R_CLK
FF_STA[2:0]
001 (Empty)
010 (Almost Empty)
Fig. 11 FIFO Empty to Almost Empty Write Timing
PCLK_IN DATA_OUT[19:10] (LUMA) WEN
WORD27
WORD28
WORD29
WORD30
WORD31
WORD32
(Low)
R_CLK FF_STA[2:0]
010 (Almost Empty) 011 (Ready)
Fig. 12 FIFO Almost Empty to Ready Write Timing
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PCLK_IN DATA_OUT[19:10] (LUMA) WEN
WORD503
WORD504
WORD505
WORD506
WORD507
WORD508
(Low)
GS1500
R_CLK FF_STA[2:0]
011 (Ready) 100 (Half Full)
Fig. 13 FIFO Ready to Half Full Write Timing
PCLK_IN DATA_OUT[19:10] (LUMA) WEN
WORD983
WORD984
WORD985
WORD986
WORD987
WORD988
(Low)
R_CLK FF_STA[2:0]
100 (Half Full) 101 (Almost Full)
Fig. 14 FIFO Half Full to Almost Full Write Timing
PCLK_IN DATA_OUT[19:10] (LUMA) WEN
WORD 1016 WORD 1017 WORD 1018 WORD 1019 WORD 1020 WORD 1021 WORD 1022
R_CLK FF_STA[2:0]
101 (Almost Full) 110 (Full) 111 (Write Error) 110 (Full)
Fig. 15 FIFO Almost Full to Full to Write Error Timing
PCLK_IN R_CLK FFRST REN/WEN
At least 5 cycles of slowest clock
High for at least 1 cycle after FFRST toggles
Fig. 16 Recommended External FIFO Reset Process
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PCLK_IN DATA_OUT[19:10] (LUMA) ANC_DATA_Y DATA_OUT[9:0] (CHROMA) ANC_DATA_C
3FF 000 000 XYZ (EAV-ID) CLN0 CLN1 CCCR0 000 3FF 3FF DID CS 3FF 000 000 XYZ (EAV-ID) YLN0 YLN1 YCCR0 000 3FF 3FF DID CS
GS1500
Fig. 17 ANC_DATA_Y and ANC_DATA_C Timing
PCLK_IN DATA_OUT[19:10] (LUMA) DATA_OUT[9:0] (CHROMA) YCS_ERR
DC
UDDC
UDDC-1
UD2
UD1
CSY
Y0
Y1
Y2
DC
UDDC
UDDC-1
UD3
UD2
UD1
CSC
C0
C1
CCS_ERR
Fig. 18 YCS_ERR and CCS_ERR Timing
PCLK_IN DATA_OUT[19:10] (LUMA) LINE_CRC_ERR_Y DATA_OUT[9:0] (CHROMA)
XYZ (EAV-ID) XYZ (EAV-ID)
3FF
000
000
YLN0
YLN1
YCCR0
YCCR1
3FF
000
000
CLN0
CLN1
CCCR0
CCCR1
LINE_CRC_ERR_C
Fig. 19 Luma and Chroma LINE_CRC_ERR Timing
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PACKAGE DIMENSIONS
23.20 0.25 20.0 0.10 18.50 REF
GS1500
12 TYP 17.20 0.25 12.50 REF 14.0 0.10 0-7 0.13 MIN. RADIUS 1.6 REF 3.00 MAX 0.88
0.15
0.75 MIN 0 -7 0.30 MAX RADIUS
128 pin MQFP
0.50 BSC 0.27
0.08
2.80 0.25
All dimensions in millimetres
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change.
REVISION NOTES: Updated Absolute Maximum Ratings; Updated AC and DC Electrical Characteristics Tables; Added information to FIFO section; Updated Figures 4 and 6.
For latest product information, visit www.gennum.com
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright August 1999 Gennum Corporation. All rights reserved. Printed in Canada.
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